1. Field of the Invention
The present invention relates to up/down counters and more particularly to an up/down counter to alternatively count up then count down pulses of successive pulse trains.
2. Discussion of the Related Art
FIG. 1 schematically represents four pulse trains of a signal B. Signal B is applied to the counting input of a conventional up/down counter. Such an up/down counter conventionally has an input U/D for switching the counter to up counting or down counting mode. FIG. 1 also represents the waveform of a signal U/D, for example, to count up pulses of trains of an odd rank and to count down pulses of trains of an even rank. The state of signal U/D switches at each end of a pulse train. More generally, signal U/D could switch at any time between two pulse trains.
Such a counting mode allows, for example, for determining the difference in width of two successive low frequency pulses by observing and resetting the content of the up/down counter at each even number of low frequency pulses. To obtain signal B, a high frequency clock signal and low frequency pulses to be measured are combined in a logic gate. Of course, the up/down counter must operate at the high frequency clock signal. The architecture of conventional up/down counters is synchronous, that is, such counters include a plurality of flip-flops, that are all controlled by a counting signal. The fact that the state of a flip-flop is changed or unchanged during a counting signal pulse is defined by peripheral logic circuits. In a first type of conventional synchronous up/down counter, for example, such as the counter referenced SN74HC191 of Texas Instruments, the peripheral logic circuits include, for each flip-flop of rank N, a Logic gate with N-1 inputs. In CMOS technology, the duration of the switching depends on the square of the number of inputs. The switching of any of such multi-input gate determines the change of state of the corresponding flip-flop. Thus, the maximum frequency of this type of up/down counter is limited by the switching time of the gate having the higher number of inputs (N-1).
FIG. 2 represents an alternative architecture of a synchronous up/down counter. The up/down counter is represented in a count-down configuration. Such bit up/down counter is comprised of N identical cascade-connected cells. Each cell includes a D-type flip-flop 10, a 2-input Exclusive NOR gate 12, and a 2-input AND gate that is conventionally formed by an NAND gate 14 followed by an inverter 15. Flip-flop 10 is connected to a counting line CK that is common to all of the flip-flops. The output of the Exclusive NOR gate 12 is connected to the data input D of the flip-flop. The two inputs of the NOR gate 12 are connected in parallel with two inputs of the NAND gate 14. The output of gate 14/15 provides a carry signal C (C.sub.0, C.sub.1, C.sub.2. . . ) to one of the common inputs of gates 12 and 14 of the cell of the higher rank. For the cell of the first rank, this common input receives a "1". The second common input of gates 12 and 14 is connected to the inverted output Q* of flip-flop 10.
In counting mode, as represented in dotted lines in FIG. 2, the output of the Exclusive NOR gate 12 is connected to the data input D of the flip-flop through an inverter 16; the non-inverted output Q is connected to this second common input; the Q outputs of the flip-flops determine the state of the counter.
The description of the operation of the circuit of FIG. 2 is not useful to the present disclosure: however, it should be reminded that in some cases, the "1" present at the input of the first gate 14 must be transmitted to the last gate 14 before the arrival of the next pulse on line CK. This occurs, for example, in counting down mode, when the state of the counter goes from state 1000 . . . to state 0111 . . . Thus, the counting frequency of such a counter is limited by 2(N-1) switching times of the gate for an N-bit counter.
In practice, the architecture of FIG. 2 is faster than the architecture of counter SN74HC191 for a large number of bits. In a conventional CMOS technology, a 10-bit counter implementing this architecture has a limit frequency of approximately 42 MHz.
FIG. 3 represents a conventional architecture of an asynchronous counter. Such a counter includes a plurality of cascade-connected D-type flip-flops. The clock input of each flip-flop is connected to the non-inverted output Q of the preceding flip-flop, and the clock input of the first flip-flop receives the counting signal CK. Each flip-flop is connected according to a divider by 2 configuration, i.e., the inverted output Q* of the flip-flop is connected to the data input D of the flip-flop. With this configuration, when a flip-flop receives an active edge, generally a rising edge, at its clock input, it memorizes the state of its inverted output Q*, i.e., the content of the flip-flop is inverted. In such a counter, whose flip-flops are enabled by rising edges, if the non-inverted outputs Q are selected as output, the counter counts down; if the inverted outputs Q* are selected as output, the counter counts up.
The advantage of an asynchronous counter such as the counter of FIG. 3 is that its limit frequency is the limit frequency of the first flip-flop. In conventional CMOS technology, a D-type flip-flop has a limit frequency of approximately 100 MHz.
However, an asynchronous counter does not allow, for example, to count up to a predetermined value, then to count down from this value. Therefore, such a counter cannot be used directly to count up and to count down successive pulse trains.